1. Field of the Invention
The present invention relates to a display panel driving apparatus and a design method therefor and, more particularly, to a ramp reset waveform generation apparatus of a display panel which efficiently generates a ramp reset waveform of a plasma display panel, and a design method therefor.
2. Description of the Related Art
In general, a plasma display panel (PDP) is a flat panel display for displaying characters or images using plasma generated by gas discharge. Depending on the size of the PDP, pixels ranging from several hundreds of thousands to more than millions are arranged in a matrix form.
The basic operation of a PDP driving circuit is explained in U.S. Pat. No. 4,866,349.
The driving sequence of a PDP is divided into a reset period, an address discharge period, and a sustain discharge period. In the reset period, all cells are discharged and, at the same time, wall charges are erased such that the display history is erased. In the address discharge period, discharge cells are selected from a matrix formed by the combination of row/column electrodes so that address discharge is formed. In the sustain discharge period, sustain discharge and energy recovery are repeatedly performed only in cells forming wall charges to display images.
More specifically, the reset period includes a wall charge erase period for which wall charges that are remaining, after finishing the sustain discharge of the previous field, are erased, and a wall charge rearrangement period initializing the panel for addressing of a current field.
Waveforms used for resetting in a PDP panel include an exponential waveform, a square waveform, a ramp waveform, and so on. Using a square-waveform pulse to reset has an advantage in that the implementation of a driving circuit is very simple. However, the quality of the contrast ratio is degraded due to the strong discharge generation. Using an exponential waveform to reset has other drawbacks, in that, the resetting time is long and an optimal reset is difficult to achieve. Because an exponential waveform reset is performed by charging the capacitance of a panel through a resistor, heat is generated and efficiency degrades due to the power consumed by the resistor.
Ramp waveform reset compensates for these problems and, at present, is the most widely used resetting function in PDP driving circuits.
FIG. 1 is a schematic diagram of a prior art structure of an alternating current (AC) PDP driving system implementing a reset function using a ramp waveform, and FIG. 2 shows the driving waveforms as applied to electrodes X and Y of a PDP.
The operation of ramp circuits A, B and C shown in FIG. 1 are basically identical and, except for devices with auxiliary purposes, can be diagramed as illustrated in FIG. 3.
The capacitance of the panel is denoted by Cp, and it is assumed that the initial voltage across Cp is 0V. A power source V+ determines the final value of a ramp waveform, for example, VE or VSET. The power source V+ determines only the final value of the ramp and is independent to the generation of the ramp waveform. The power source V+ charges capacitor CR before the ramp generation signal VG is applied. If voltage is applied to VG, a portion of current iR flows into the gate of MOSFET MR and increases gate-source voltage VGS. The remaining portion of current iR flows into capacitor CR. Once enough charge has accumulated in the gate of MR and VGS exceeds a threshold voltage VTH, MR exits a cut-off state and current iD begins to rapidly increase and may be represented as a quadratic function. At this time, the charging of CP is performed at full scale. Once the rate of charging of CP by current iD−iR equals the rate of discharging of CR by current iR−iG, VGS will be in equilibrium. If VGS is in equilibrium, drain current iD of MR is maintained and, at the same time, other currents on the circuit are maintained such that the voltage across CP increases linearly. If drain current iD temporarily increases and CP charges faster than the discharge rate of CR, VGS will decrease and the drain current iD will again decrease such that the rate of the voltage increase of CP is reduced. Also, if VGS decreases, a current flowing into CR will increase and the discharge rate of CR will increase such that the rate of change of the voltages across CP and CR are maintained identically. The value of resistor RG determines a normal state value of VGS and, by adjusting resister RG, the slope of the voltage waveform across CP can be adjusted.
In the circuit structure of FIG. 3, MOSFET MR does not work as a switching device but as a voltage-controlled current source, which plays the role of a variable resistor. Therefore, efficiency is degraded due to heat generation and a heat radiation plate is required. In addition, ramp generation circuits are allocated for each ramp waveform, and respective power sources are required for the final values of different ramp waveforms. Thus, the system structure is complicated, which increases the cost of materials for manufacturing.